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-1- NJU3426 ver.2003-09-02 16-segment x 14-digit vfd controller / driver general description the NJU3426 is a vfd (vacuum fluorescent display) controller/driver to dynamically drive up to 16 segments x 14 digits. it consists of display data ram, an address counter, command registers, a serial interface and high voltage drivers. the NJU3426 features the direct connection to mpu and the high voltage drivers of 45v well-suited for various vfd displays. features directly drives 16-segment x 14-digit high vfd driving voltage : |v dd -v fdp | 45v display shift function programmable duty ratio for timing signal :2/16, 4/16, 6/16, 8/16, 10/16, 12/16, 14/16, 15/16 duty display on/off control function display data ram : 30 x 8-bit built-in oscillator (external ceramic resonator or external resistor or external clock) 8-bit serial interface power-on reset function operating voltage : 3.3v / 5.0v c-mos technology package outline :qfp48-p1 block diagram package outline NJU3426fp1 xt xtb si sck rstb csb t 0 to t 13 segment data latch osc timing counter v dd v ss v fdp serial buffer high voltage driver timing counter s 0 to s 15 rest display ram 30 x8-bit address counter character address counter instruction decoder duty counter high voltage driver initial character address counter
- 2 - NJU3426 ver.2003-09-02 pin configuration terminal discription pad no. symbol function 48 v dd power supply for logic voltage 3.3v / 5.0v 45 v ss ground v ss =0v 39 v fdp power supply for vfd driving voltage 46 47 xt xtb ceramic resonator connection, resistor connection, or external clock input the internal oscillator is formed by connecting an external ceramic resonator to these pins. when an external oscillator is used instead of the internal oscillator, the external clock is input to the xt and the xtb must be open. 3 to 12, 15 to 20 s 0 to s 15 segment output terminals (pulled down) 21 to 24, 27 to 36 t 0 to t 13 timing output terminals (pulled down) 41 rstb reset terminal (pulled up) active ?l?: reset is executed when this pin is ?l?. reset does not change the contents of display data ram. 42 csb chip select active ?l?: data transmission is enable when this pin is ?l?. 43 sck serial clock input 44 si serial data input (8 bits = 1 word) 1, 2, 13, 14, 25, 26, 37, 38, 40 n.c. non connections these pins must be open. v fdp n.c. rstb csb sck si v ss xt xtb v dd t 11 t 12 t 13 n.c. s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 n.c. n .c. n .c. s 8 t 5 t 6 t 7 t 8 t 9 t 10 3 2 1 6 5 4 9 8 7 29 28 11 10 39 31 30 33 32 35 34 36 38 37 40 41 42 43 44 45 46 47 48 NJU3426fp1 n.c. s 9 n.c. n .c. n .c. t 4 12 26 25 14 13 16 15 18 17 20 19 22 21 23 24 27 t 3 t 2 t 1 t 0 s 15 s 14 s 13 s 12 s 11 s 10
-3- NJU3426 ver.2003-09-02 function description (1) address counter the address counter specifies the ?display data ram address?, and the display data is transferred to or from this address. for the data transmission, once an initial ram address is determined, the display data can be continuously transmitted without setting the ram address. when the upper 2 bits (b7 and b6) of the 1st word are ?0,0?, the lower 5 bits (b4 to b0) are interpreted as ram address data. and the 2nd word is interpreted as display data which is stored in the ram address specified by the 1st word, and simultaneously the ram address is counted up. although the ?display data ram address? can be set only in the range of ?0,0,0,0,0? (00 h ) and ?1,1,1,0,1? (1d h ), the auto-increment keeps counting up to ?1,1,1,1,1? (1f h ), and the ram address finally wraps to ?0,0,0,0,0? (00 h ) then begins counting up. note that the display data, specified to the ram address of ?1,1,1,1,0? (1e h ) or ?1,1,1,1,1? (1f h ), is ignored in this sequence. display data ram address *:don?t care character address b7 b6 b5 b4 b3 b2 b1 b0 ram address b7 b6 b5 b4 b3 b2 b1 b0 c 0 01 h 00 h t 0 c 1 03 h 02 h t 1 c 2 05 h 04 h t 2 c 3 07 h 06 h t 3 c 4 09 h 08 h t 4 c 5 0b h 0a h t 5 c 6 0d h 0c h t 6 c 7 0f h 0e h t 7 c 8 11 h 10 h t 8 c 9 13 h 12 h t 9 c 10 15 h 14 h t 10 c 11 17 h 16 h t 11 c 12 19 h 18 h t 12 c 13 1b h 1a h t 13 c 14 1d h 1c h 1f h 1e h s 15 s 14 s 13 s 12 s 11 s 10 s 9 s 8 s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 : non-existent address display data ram map b7 0 recognition data b6 0 b5 * b4 ad4 b3 ad3 b2 ad2 b1 ad1 b0 ad0 display data ram address ram address
- 4 - NJU3426 ver.2003-09-02 (2) command register 1 the ?command register 1? is used for setting ?duty ratio for timing signal?, ?display control on/off? and ?shifting display digits?. when the upper 1 bit (b7) of the 1 st word is ?1?, the lower 7 bits (b6 to b0) are interpreted as command data, and stored in the ?command register 1?. the contents of the ?command register 1? are initialized to the default values by the power-on reset or the reset signal, as shown below. de fault values of command register 1 ? duty ratio for timing signal : 2/16 ? display control on/off : off ? shifting display digits : 7 dt2 dt1 dt0 duty ratio for timing signal 0 0 0 2/16 0 0 1 4/16 0 1 0 6/16 0 1 1 8/16 1 0 0 10/16 1 0 1 12/16 1 1 0 14/16 1 1 1 15/16 note.) the output waveforms of timing signal are shown in ? ? ? ? ? timing signal / duty-change waveform ?. dsp display control 0 off 1 on note.) when the ?display control off? is set, segment drivers output waveforms but all timing signal outputs are halted de2 de1 de0 shifting display digits 0 0 0 7 0 0 1 8 0 1 0 9 0 1 1 10 1 0 0 11 1 0 1 12 1 1 0 13 1 1 1 14 b7 1 recognition data b6 d t2 b5 d t1 b4 d t0 b3 dsp b 2 de2 b1 de1 b0 de0 duty ratio for timing signal display control on / off shifting display digits
-5- NJU3426 ver.2003-09-02 (3) command register 2 the ?command register 2? is used for setting the ?initial character address?, which corresponds to the t 0 pin. when the upper 2 bits (b7 and b6) of the 1 st word is ?0,1?, the lower 4 bits (b3 to b0) are interpreted as command data and stored in the ?command register 2?. the contents of the ?command register 2? are initialized to the default values by the power-on reset or the reset signal, as shown below. de fault values of command register 2 ? initial character address : c1 (0,0,0,1) *:don?t care ds3 ds2 ds1 ds0 initial character address 0 0 0 0 c 0 0 0 0 1 c 1 0 0 1 0 c 2 0 0 1 1 c 3 0 1 0 0 c 4 0 1 0 1 c 5 0 1 1 0 c 6 0 1 1 1 c 7 1 0 0 0 c 8 1 0 0 1 c 9 1 0 1 0 c 10 1 0 1 1 c 11 1 1 0 0 c 12 1 1 0 1 c 13 1 1 1 0 c 14 1 1 1 1 prohibited b7 0 recognition data b6 1 b5 * b4 * b3 ds3 b2 ds2 b1 ds1 b 0 ds0 initial character address
- 6 - NJU3426 ver.2003-09-02 (4) display shift operation the display shift operation is performed by changing the ?initial character address? of the ?command register 2?. and the number of digits for the display shift in the loop is determined by the ?shifting display digits? of the ?command register 1?. in other words, shifting display area ranges from the ?initial character address? specified by the ?command register 2? to the last address specified by the ?command register 1?. the default value of the ?initial character address? is c 1 (0,0,0,1), as shown in the table of ?display data ram?. in addition, supposing that the value of the ?shifting display digits? is ?n?, the ?initial character address? should be set in the range of c 0 and c n in order not to exceed the digit ?n?. because the display shift operation is not applied to the addresses beyond the digit ?n?, the display images, which were initially set up, appear on these addresses. just for reference, one character of display image is composed of 16 segments. how to set left display shift the left display shift is carried out by incrementing the ?initial character address? gradually like c 2 , c 3 , c 4 , --- c n . to the contrary, decrementing the address performs right display shift. the following description shows the example on how to set the left display shift, using alphanumeric display images such as ?0?, ?1?, ?2?, ---, ?9?, ?a?, ?b?, ---, and ?e?. step1) setting display images in the display data ram ? display ram data character address c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 14 display image 0 1 2 3456789ab c d e setp2) setting the ? initial character address ? to c 2 and the ? shifting display digits n ? to 12 (t 11 ). is not shifted. in this setting, the display images of "2", "3?,- - - appear on the t 0 , t 1 , t 2 , - - - t 10 pins respectively, and the image ?0? is on the t 11 pin, which is assigned to the 12 th character address. the display images ?d? and ?e? don?t shift but remain on the t 12 and t 13 pins, assigned to the 13 th and 14 th characters respectively, because their character addresses are outside the digit ?n?. step3) changing the ? initial character address ? to c 3 , and leaving the ? shifting display digits n ? as 12 (t 11 ). is not shifted. shifting display digits c 1 c 2 c 3 c 0 c 13 c 14 t 0 t 1 t 10 t 11 t 12 t 13 c 12 character address timing output terminals character display image 1 2 11 12 13 14 shifting display digits c 2 c 3 c 4 c 1 c 13 c 14 t 0 t 1 t 10 t 11 t 12 t 13 c 0 character address timing output terminals character display image 1 2 11 12 13 14
-7- NJU3426 ver.2003-09-02 timing signal / duty-change waveform display timing chart oscillation frequency : f xt :800khz to 3.5mhz minimum blanking time : t bk =(1/f xt ) x 16 x 2 :40 s to 9.14 s (duty15/16) 1-character display time : t dg =t bk x 16 :640 s to 146.28 s 1-cycle display time : t sp =t dg x 14 :8.96ms to 2.05ms display timing (duty count) timing signal (t 0 to t 13 ) segment signal 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 dt1 dt0 dt2 0 0 0 2/16 0 1 0 4/16 1 0 0 6/16 1 1 0 8/16 0 0 1 10/16 0 1 1 12/16 1 0 1 14/16 1 1 1 15/16 f xt t bk t dg ? ? ? ? t sp xt t 0 t 1 t 2 t 13 s 0 to s 15 ? ? ? ?
- 8 - NJU3426 ver.2003-09-02 (5) serial data transmission communication between the NJU3426 and mpu uses the serial data transmission with synchronous clock, and 8 bits serial data constitutes 1 word. each bit on the si pin is latched at the rising edge of the serial clock (sck), and the entire 8 bits are loaded as 1 word at the rising edge of the chip select (csb). during a data transmission, multiple words are transferred continuously. the 1 st word is either ?display data ram address?, ?command register 1? or ?command register 2?. when the 1 st word is ram address data, the 2 nd and ascending words are interpreted as display data. when it?s the ?command register 1 or 2?, the 2 nd and ascending words are ignored. serial data timing serial data transmission format ? serial input data data format for the 1 st word display data ram adress b7 b6 b5 b4 b3 b2 b1 b0 0 0 * ad4 ad3 ad2 ad1 ad0 *:don?t care command data 1 b7 b6 b5 b4 b3 b2 b1 b0 1 dt2 dt1 dt0 dsp de2 de1 de0 *:don?t care command data 2 b7 b6 b5 b4 b3 b2 b1 b0 0 1 * * ds3 ds2 ds1 ds0 *:don?t care serial data for the 2 nd and ascending words when the 1 st word is the ?display data ram address?, the 2 nd and ascending words are interpreted as display data. when the 1 st word is the ?command register 1 or 2?, the 2 nd and ascending words are ignored. sck si d0 d1 d2 d3 d4 d5 d6 d7 sck word 1 word 2 word n csb si
-9- NJU3426 ver.2003-09-02 absolute maximam ratings (v ss =0v, ta=25 c) parameter symbol ratings unit conditions supply voltage v dd -0.3 to +7.0 v input voltage v in -0.3 to v dd +0.3 v vfd driving voltage v fdp v dd -45 to v dd +0.3 v relative to v dd . ?h? level output current 1 i oh1 -15 ma 1 pin out of s 0 to s 15 pins ?h? level output current 2 i oh2 -35 ma 1 pin out of t 0 to t 13 pins ?l? level output current i ol 20 ma operating temperature topr -40 to 85 c storage temperature tstg -55 to 125 c power dissipation pd 1500 mw on two-layer board of based on the jedec. note 1): the lsi must be used inside the ?absolute maximum ratings?. otherwise, an electrical or physical stress may cause a permanent damage to the lsi. note 2): de-coupling capacitors should be placed on v dd and v ss and v fdp and v ss for stable operation. note 3): the following voltage relation must be maintained; v dd > v ss v fdp , v ss =0.
- 10 - NJU3426 ver.2003-09-02 electrical characteristics ? dc characteristics 1 (v dd =5.0v, v ss =0v, ta=-40 to 85 c) parameter symbol conditions min typ max unit operating voltage v dd v dd terminal 4.5 5.5 v ?h? level input voltage v ih 0.8v dd ?l? level input voltage v il xt, rstb, csb, sck, si terminals 0.2v dd v input off leak current i iz csb, sck, si terminals v dd =5.5v, v i =0 or 5.5v 1 a s o to s 15 terminals -4.5 -9 ma display output current i oh t o to t 13 terminals v dd =4.5v, v fdp =v dd -40v, v oh =v dd -2.5v -10.5 -21 ma pull-up resistance r ur rstb terminal, ta=25 c, v i =v ss 100 280 k ? pull-down resistance r dst s 0 to s 15 , t 0 to t 13 terminals, ta=25 c v i =v dd , v fdp =v dd -40v 60 160 k ? logic operating current i ss v ss terminal, all segment/timing output terminals open, rstb terminal open, ceramic resonator:1mhz, all segment output off and all timing output off 1 2 ma display operating current i fdp v fdp terminal, v fdp =v dd -40v, ceramic resonator:1mhz, all segment/timing output on 10 15 ma ? ac characteristics 1 (v dd =5.0v, v ss =0v, ta=-40 to 85 c) parameter symbol conditions min typ max unit operating oscillation frequency f xt fig. 1 0.8 3.5 mh z cr oscillation frequency * f cr ta=25 c r f =27k ? 0.85 1 1.15 mhz external clock input rise time, fall time t clh , t cll fig. 2 250 *) ns serial input data setup time t sis fig. 2 35 ns serial input data hold time t sih fig. 2 35 ns serial clock frequency f sck fig. 3 1.5 mh z serial clock interval time t sci fig. 3 10 s reset palse width t rstb fig. 4 10 s power rise time t r fig. 5 0.05 10 ms *) noises on sck during rise time or fall time may cause malfunctions. testing samples in the application is recommended.
-11- NJU3426 ver.2003-09-02 ? dc characteristics 2 (v dd =3.3v, v ss =0v, ta=-40 to 85 c) parameter symbol conditions min typ max unit operating voltage v dd v dd terminal 3.0 3.6 v ?h? level input voltage v ih 0.8v dd ?l? level input voltage v il xt, rstb, csb, sck, si terminals 0.2v dd v input off leak current i iz csb, sck, si terminals v dd =3.6v, v i =0 or 3.6v 1 a s 0 to s 15 terminals -2 -4 ma display output current i oh t 0 to t 13 terminals v dd =3.0v, v fdp =v dd -40v, v oh =v dd -1.5v -4.5 -9 ma pull-up resistance r ur rstb terminal, ta=25 c, v i =v ss 100 280 k ? pull-down resistance r dst s 0 to s 15 , t 0 to t 13 terminals, ta=25 c v i =v dd , v fdp =v dd -40v 60 160 k ? logic operating current i ss v ss terminal, all segment/timing output terminals open, rstb terminal open, ceramic resonator:1mhz, all segment output off and all timing output off 0.8 1.5 ma display operating current i fdp v fdp terminal, v fdp =v dd -40v, ceramic resonator:1mhz, all segment/timing output on 10 15 ma ? ac characteristics 2 (v dd =3.3v, v ss =0v, ta=-40 to 85 c) parameter symbol conditions min typ max unit operating oscillation frequency f xt fig. 1 0.8 2 mh z cr oscillation frequency * f cr ta=25 c r f =18k ? 0.85 1 1.15 mhz external clock input rise time, fall time t clh , t cll fig. 2 250 *) ns serial input data setup time t sis fig. 2 70 ns serial input data hold time t sih fig. 2 70 ns serial clock frequency f sck fig. 3 0.8 mh z serial clock interval time t sci fig. 3 10 s reset palse width t rstb fig. 4 20 s power rise time t r fig. 5 0.05 5 ms *) noises on sck during rise time or fall time may cause malfunctions. testing samples in the application is recommended.
- 12 - NJU3426 ver.2003-09-02 * relation between external resistor (r f ) and oscillation frequency (f cr ). the frequency can be adjusted by the selection of external resistor r f , as shown in ?r f vs f cr ?. refer to circuit example of ? ? ? ? ? application circuit (b) cr oscillation?. r f vs f cr 0 1 2 3 4 0 10203040 vdd=5.0v vdd=3.0v this graph shows a reference characteristic, and this performance is not guaranteed. r f [k ? ] f cr [mhz]
-13- NJU3426 ver.2003-09-02 fig. 1 fig. 2 fig. 3 fig. 4 fig. 5 90% 10% t r v dd t rstb rstb v il v il 50% 50% 50% 50% t sci f sck csb sck t sci 50% t sci f xt v ih v ih xt v ih v ih v il v il t sis t sih sck si t clh t cll v ih v ih v il v il
- 14 - NJU3426 ver.2003-09-02 application circuit (a) ceramic resonator oscillation cpu vfd c2 c1 v dd v fdp c0 c0 r v fdp n .c. rstb csb sck si v ss xt xtb v dd t 11 t 12 t 13 n.c. s 7 s 6 s 5 s 4 s 3 s 2 s 1 n.c. n.c. s 8 t 5 t 6 t 7 t 8 t 9 t 10 NJU3426fp1 n.c. s 9 n.c. n .c. n .c. t 4 t 3 t 2 t 1 t 0 s 15 s 14 s 13 s 12 s 11 s 10 s 0 n.c.
-15- NJU3426 ver.2003-09-02 (b) ceramic resonator oscillation cpu v dd v fdp c0 r f v fdp n .c. rstb csb sck si v ss xt xtb v dd t 11 t 12 t 13 n.c. s 7 s 6 s 5 s 4 s 3 s 2 s 1 n .c. n.c. s 8 t 5 t 6 t 7 t 8 t 9 t 10 NJU3426fp1 n.c. s 9 n.c. n .c. n .c. t 4 t 3 t 2 t 1 t 0 s 15 s 14 s 13 s 12 s 11 s 10 vfd c0 s 0 n.c. [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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